The recent miniaturization of DRAM (Dynamic Random Access Memory) cells has been accompanied by the necessity of shortening the gate length of access transistors (hereinafter referred to as cell transistors) in cell arrays. However, short channel effects in a transistor become more severe as the gate length is shortened, and drawbacks occur whereby the threshold voltage (Vt) of the transistor is reduced by increased sub-threshold current. When the impurity concentration in the substrate is increased in order to minimize the decrease in Vt, deterioration of the refresh characteristics in the DRAM becomes a severe drawback because of increased junction leakage.
Making the source/drain region of a cell transistor asymmetrical (asymmetric transistor) is known as one method for enhancing refresh characteristics in DRAM. This method involves restricting the spread of a depletion layer and preventing punch-through by making the concentration of an N-type impurity in the source/drain region on the bit line side higher than the concentration thereof in the source/drain region on the storage node side, and selectively forming a highly concentrated P-type impurity region below the source/drain region on the bit line side (see Japanese Patent Application Laid-open No. H05-102479). Maintaining a low impurity concentration in the substrate also makes it possible to minimize junction leakage in the source/drain region on the storage node side.
In this type of asymmetric transistor structure, after first forming a gate electrode on a P-type silicon substrate by a publicly known method, the region in which the source/drain region is to be formed on the storage node side is masked with a photo-resist, and a high-density P-type diffusion layer is formed by ion implantation of boron (B) deeper than the source/drain region, after which arsenic (As) is ion implanted to form a high-density N-type diffusion layer above the high-density P-type diffusion layer. A so-called punch-through stopper region is thereby formed. This region is composed of a high-density P-type diffusion layer that is below and adjacent to a source/drain region composed of a high-density N-type diffusion layer on the bit line side. The photo-resist is then completely removed, and phosphorus (P) is ion implanted on the entire surface of a P-type silicon substrate using the gate electrode as a mask, whereby a source/drain region on the storage node side is formed. This region is composed of a low-density N-type diffusion layer.
As described above, in order to form a source/drain region that has an asymmetric structure, a source/drain region must be formed using a photo-resist as a mask. However, since the aspect ratio of the space between gate electrodes has increased in conjunction with recent advances in pattern miniaturization and reduced transistor gate length, drawbacks are created by the photo-resist 107 remaining after photolithography, as shown in FIG. 12. In particular, the aspect ratio is further increased by polymetal gates and other multilayer structures such as those involving the gate electrodes 112, and photo-resist residues are a severe drawback. The photo-resist 107 acts as a mask for ion implantation when forming the high-density N-type diffusion layer (source/drain region on bit line side) and high-density P-type diffusion layer (punch-through stopper region) of an asymmetric transistor. It is therefore impossible to perform ion implantation with high precision in the prescribed profile when the photo-resist 107 forms a residue in this manner.